Modern integrated sensors contain a small data memory of the size of 10 bits to 1000 bits to store the calibrating data of a sensor on the chip therewith. For automotive applications, high reliability is demanded so that it is required to guarantee the integrity of the data with known methods of error detecting and error correcting codes (FEC codes=forward error correcting codes).
Since the memory size is therefore very small as compared to data preservation systems common today and, on the other hand, reasons of economy force designers to implement a system as simple as possible, the matrix parity check is widely used as FEC method. In order to explain the matrix parity check in more detail, a memory 600 is symbolically illustrated in FIG. 6. The memory 600 has a word width of 16 bits, wherein the individual bits of the words are designated by the bit numbers 602, as illustrated in the row above memory 600 in FIG. 6 (i.e. the columns 0 to 15 designate the individual bits of the corresponding words). The memory 600 further includes an address area of 15 words, wherein each word may be written into a row 604, whereby the 15 words in the memory 600 may be addressed by the row address addr_i=0 . . . 14. The division into two data areas (user and precal data) may be ignored here. Row parity bits are stored on the address 0, corresponding column parity bits are stored on the column 15 indicated by the reference numeral 606. Furthermore, the designation “row parity” (reference numeral 608) represents the calculated parity per row (which, however, is not stored, but calculated when reading out a row). Likewise, “column parity” (reference numeral 601) represents the calculated parity per column (which is not stored either, but calculated when reading out the row).
The operation of the above matrix parity check may be described as follows. The calibrating data required for a sensor are programmed into the addresses 1 to 14 and the columns 0 to 14. Each word is provided with a parity bit, which is programmed in the column 15. The parity bit is to be selected so that the number of ones per row is even (=even parity). The parity row—i.e. the totality of all column parity bits—is stored in address 0; it is calculated so that the number of ones per column is also even. It is to be noted here that the parity of all cells of a column (i.e. for the rows 1 . . . 15) is referred to as column parity, and the parity of all cells of a row (i.e. for all columns 0 . . . 15 of a row) is referred to as row parity. In contrast, the row containing no data, but only column parity bits, i.e. which contain redundancy information for error detection and correction (stored in the address 0 in the example), is referred to as parity row. Analogously, the column containing no data, but only row parity bits containing redundancy information for error detection and/or correction (the column with the address 0 in the example) is referred to as parity column.
When reading out the data, the number of ones per column and row is counted. If it is odd, at least one bit in the corresponding row or column must be toggled, as it is illustrated, for example, in FIG. 7 with respect to the bit in column number 7 and row number 10. Technically, counting the number of ones in the whole memory is complicated. Therefore, only the number of ones per column is calculated continuously by combining the bits of a column with an EXCLUSIVE-OR gate (for example in the form of a hard-coded logic). This means that, for example, the bit of address 0, column 7 is combined with the bit of address 1, column 7, the bit of address 2, column 7, . . . , and the bit of address 14, column 7, by an EXCLUSIVE OR operation to achieve the bit in the column parity row (i.e. the bit number 7 of row 610) for column 7. Formally, such an operation may be illustrated as follows:    Bit (address 0, column 7) ⊕ bit (address 1, column 7) ⊕ . . . ⊕ bit (address 14, column 7)=column parity <7>. Here, the symbol ⊕ means an XOR operation (=EXCLUSIVE-OR operation) equaling an addition modulo 2. If column parity <7>=0, the number of ones in column 7 is even, i.e. no bit error has been detected in this column.
If column parity <7>=1, the number of ones in column 7 is odd, i.e. a bit error has been detected in this column. When reading out a row—as marked by the highlighted address row 10 in FIG. 7—it is copied into a readout register 612, where all cells of this register are XORed (=EXCLUSIVE-ORed) to calculate the row parity. Formally, such an operation for determining the row parity bit 614 may be described by the following equation:Row parity=bit <0> ⊕ bit <1> ⊕ . . . ⊕ bit <15>.
Furthermore, FIGS. 6 and 7 also illustrate how, in the case of an error detection (i.e. when row parity=1), a detected error may be corrected automatically. This is done by combining the row parity bit 614 with an error correction enable signal fec_en_i in an AND gate 616, wherein the error correction enable signal assumes a logic value of 1 when a forward error correction is to be performed. The signal resulting from the AND gate 616 is used as input signal of a further AND gate 618 at whose second input the values of the column parity 610 are applied so that, as output signal of the AND gate 618, a 16 bit wide word is output in which the places in the corresponding address row addr_i which are to be corrected are coded with a binary value of 1, while the places not to be corrected are coded with the binary value of 0. This output signal of the AND gate 618 is then supplied as an input signal to an EXCLUSIVE-OR gate 620, at the second input of which the 16 bit wide word from the register 612 is applied. A column-wise EXCLUSIVE-OR operation is performed, wherein the correspondingly toggled bits of the word stored in the register 612 may be corrected.
By way of illustration, it is again repeated that parity actually means the number of ones in a data word. There is even parity when this number is even, otherwise there is odd parity. The memory contents thus consist of payload data and additional parity bits.
In the example described above, the row on address 0 and, in all other addresses, the column 15 were parity bits. The payload data were located in the columns 0 . . . 14 and in the rows 1 . . . 14. The parity calculation includes the payload data plus parity bit plus parity mask.
The properties of the matrix parity check for error detection may be summarized as follows. Detection is guaranteed when one or two bits are toggled; if only one bit toggles, the parity in the respective row and column is not correct, if two bits in different columns and rows are toggled, all columns and rows indicate this by an incorrect parity in the corresponding rows and columns. If two bits in the same row are toggled, the row parity is correct, but the column parity is not. Something analogous also applies to the toggling of two bits in the same column. Even when three bits are toggled, at least one toggled bit is guaranteed to be detected as faulty.
In addition, a single toggled bit may even be corrected automatically, because its position may be determined by the incorrect row and column parity, it may be inverted when read out and thus the original state may be restored (=automatic error correction).
Such a method is thus very well suited to indicate small defects concerning only a few bits and maybe even eliminate them (i.e. when only one bit is toggled). Thus, failures resulting from small defect density problems common today may be eliminated.
However, the above-described method is problematic in that the failure of the whole memory or a sub-area of the memory with an even number of rows and columns may not be detected. In the following, such a sub-area of a memory is referred to as “even block”.
Such a failure of an even block may be caused, for example, by a short circuit of all cells of a column to ground (=stuck-at-low) or to operational voltage (=stuck-at-high). It is also conceivable that the reading current for reading out the cells becomes too small or too large due to a defect, which may result in reading out all cells as digital “1” or digital “0”. Possibly, the whole memory may unintentionally be programmed to “1” or “0” by an inadmissibly high ESD (electrostatic discharge) or EMV stress (EMV=electromagnetic compatibility).
A possible solution of such problems could be to ensure, by suitable coding of the data to be stored, that the memory contents “all 1” and/or “all 0” are no valid data set, i.e. that these memory contents are never programmed. An evaluating circuit would then have to continuously read out all data in operation and sum up the number of ones and zeros. If they exceed a set limit, this is detected as an error. This evaluating circuit, however, involves a lot of effort, is complicated and error-prone (because it has to perform a large number of operating steps operating sequentially), occupies relatively much space on the chip as compared to the small data memory and is further also inefficient, because it can only detect the completely deleted or set memory, but not the failure of an even block.